The present invention relates generally to methods for formation of an upper device layer over a buried insulating layer in a semiconductor substrate, and more particularly, to methods for forming silicon-on-insulator (SOI) wafers that exhibit a high electrical resistivity.
Silicon wafers are routinely employed in the electronic industry for manufacturing a variety of integrated circuits (IC) in which a plurality of devices can be formed on a single chip. In many such applications, the silicon wafer includes an upper silicon layer, on which devices are formed, that is separated from the bulk substrate by a continuous buried silicon oxide layer. Such silicon wafers, herein referred to as SOI wafers, can be manufactured by known techniques, such as, a technique known by the acronym SIMOX (separation by implantation of oxygen). In a SIMOX process, a buried silicon oxide layer can be generated below an upper silicon layer of a wafer by implanting oxygen ions in the wafer followed by a high temperature annealing step.
The recent research efforts in developing highly integrated IC's having a multitude of active devices and passive components, including both analog and digital components positioned in close proximity of one another, have pointed the need for providing effective electrical isolation among these components. Conventional silicon wafers are, however, cut from single silicon crystals formed by a method commonly known as Czochralski (CZ) method. Such silicon wafers contain interstitial oxygen atoms with a concentration in a range of about 20–40 ppma. The concentrations cited herein are determined according to the ASTM standard. These interstitial oxygen atoms can form electrically active crystal defects known as thermal donors, especially subsequent to steps in IC manufacturing that subject the wafer to elevated temperatures, typically at temperatures between about 350 C and 600 C. Such thermal donors can reduce the wafer's electrical resistivity, and can hence adversely affect electrical isolation among different devices formed on the wafer.
Some heat treatment techniques are known for lowering the concentration of interstitial oxygen in bulk CZ silicon wafers, thereby decreasing silicon propensity for formation of thermal donors and hence maintaining electrical resistivity of the wafers above a desired high threshold. This stabilization of electrical resistivity is, however, typically lost when the wafers are subjected to a SIMOX process to form SOI wafers.
Accordingly, it is desirable to provide methods for generating SOI wafers having high, stable electrical resistivity, for example, an electrical resistivity in excess of about 100 Ohm-cm, and preferably in excess of about 500 Ohm-cm.